AES is a popular encryption standard used in several encryption schemes. AES operates on 128 bits at a time. Several AES-based encryption schemes have been developed which operate on data sizes larger than 128 bits. AES-based encryption schemes fail to provide an interface that can effectively use an AES core unit that operates on 128 bits while performing the core AES operation.
One possible solution to such a problem is to implement a direct memory access (DMA) interface around the AES core unit. Such a DMA interface is programmed by a host processor. The DMA interface can (i) fetch data from a synchronous dynamic random access memory (SDRAM), (ii) feed the data to the AES core unit, and (iii) store the encrypted/decrypted data to the SDRAM. Using such an interface, AES operation can be performed on data blocks that are much larger than 128 bits.
The main disadvantage of the DMA interface is the overhead associated with setting up the operation of the DMA interface. Designers have to program (i) the addresses of the input and output data and (ii) the sector count. The overhead is minimal if the sector size/count is large. However, in the case of an AES application where an encryption/decryption of 128 bits or 256 bits is needed, the overhead may be large when compared to the actual operation.
Another disadvantage with conventional approaches is that new AES-based encryption schemes are always being developed. Some of these schemes may include quirks that may not be supported by the DMA interface mode since the DMA interface automatically processes input data. An alternate to such an approach is to use a micro-controller to perform the entire encryption scheme in software. The use of a micro-controller may slow the encryption/decryption process down.
It would be desirable to provide a method and/or apparatus for a dual mode AES implementation to support single and multiple AES operations.